1. Field of the Invention
This invention relates to a design method used for a logical design of a semiconductor integrated circuit and to a design apparatus using this methods
2. Description of the Related Art
Generally, in a storage element for taking in an input signal at a changing point of a synchronous signal (hereinafter referred to as "clock" and holding a value of signal (hereinafter referred to as "flip-flop"), there is a possibility that a misoperation takes place when an input signal changes in a period before and after the changing point. Accordingly, in the flip-flop, the period for forbidding a change in input signal is defined for a period before and after the clock changing point as shown in FIG. 1. A period immediately before the clock changing point is called setup time and a period immediately after the clock changing point is called hold time.
Here, the circuit of FIG. 2 is taken as an example, and the case of data transfer between two storage elements will be considered. In FIGS. 2, the registers R0 and R1 represent D flip-flops, respectively. Hereinafter, the registers are represented as flip-flops. In addition, symbols D, CK and Q denote a data input pin, a clock input pin and a data output pin of the D flip-flop, respectively. Furthermore, symbol "Tpd" denotes the time taken from the input of data inputted to the data input pin of the register R0 after a change of the clock CK until the output to the data output pin Q after held in the flip-flop R0. And, symbol "Tdata" denotes the time taken after the data output pin Q of the flip-flop R0 underwent to a predetermined operation until data reaches the data input pin D of the flip-flop R1.
Meanwhile, to hold a correct value on the side of the flip-flop R1 so as to change at the same timing, all clocks under an ideal working environment must satisfy the following equation: EQU Tpd+Tdata&gt;Thold (1)
However, on an actual clock network, there is a delay originating from the influence of wiring or buffering and the length of delay differs with the respective flip-flops, so that the difference occurs in the arrival time of individual clocks. This occurrence is called "clock skew".
In FIG. 2, the clock skews of the flip-flop R0 and the flip-flop R1 are designated as a symbol of triangle (delay). This time is denoted by "Tck".
On consideration of this clock skew, the above equation (1) can be rewritten as the following equation: EQU Tpd+Tdata&gt;Thold+Tck (2)
This equation (2) represents that the hold time "Thold" of data have to be taken longer for the clock skew when there is a clock skew.
In this way, the equation (2) must be satisfied in order that data are transferred correctly between flip-flops. For this, these are several "clock skew countermeasures".
First of all, one is to reduce the hold time "Thold", another is to increase "Tpd", and another is to reduce "Tck", the other is to increase "Tdata".
Here, the first and second countermeasures, i.e., the countermeasures to reduce the hold time "Thold" and to increase the "Tpd", are characteristics intrinsic to a flip-flop and it is difficult for a designer to control them. However, if several flip-flops different in these characteristics are provided on the side of a semiconductor designer, for example, the circuit designer can approximately control these characteristics by selection of those flip-flops.
With the third countermeasure, i.e., one to reduce the clock skew, the greater the number of flip-flops is, the more difficult becomes the equal distribution of all flip-flops. As one means to achieve the third countermeasure, there is a method of self-loop connection by using a flip-flop of multi-bit configuration. However, since the bit configuration of a multi-bit flip-flop is limited in kind, selection of the most suitable combination, which group of flip-flops is allotted to the multi-bit flip-flop, is generally difficult.
The fourth countermeasure is to increase the length of delay without change in the logic between any pair of flip-flops The most simple countermeasure is achieved by inserting a non-inversional buffer. Generally, this method is often used because of being executable easier than other methods.
However, with a method or inserting a buffer between the flip-flops like the fourth countermeasure, the insertion position may becomes an issue, An effective insertion position will be thought over using a circuit example of FIGS. 3A to 3C. Here, FIG. 3A is the original circuit diagram before the insertion of a delay buffer, where the outputs of the flip-flops R0 and R1 are individually connected through the logic element U0 to the input of a flip-flop R2.
Here, because of a small delay in the logic element U0, it is assumed that a hold time violation to input from any of the flip-flops R0 and R1 takes place in the flip-flop R2.
In this case, there are two methods for inserting a delay-compensating buffer to assure the hold time.
One is a method for inserting delay buffers directly after the outputs of the flip-flops R0 and R1 as shown in FIG. 3B. This enables the hold time of both paths to be assured. At this time, two buffers are needed.
The other is a method for inserting a delay buffer directly before the input of the flip-flop R2 as shown in FIG. 3C. This method also enables the hold time of both paths to be assured, and one buffer is enough.
From a consideration of this result alone, it may be regarded as advisable to insert a delay buffer directly before a flip-flop, but such a connection is not always good. In the circuit example of FIGS. 4A to 4C, it is rather effective to insert a delay buffer directly after the output of the flip-flop R0. That is, FIG. 4A is the original circuit diagram before the insertion of the delay buffer, and the output of the flip-flop R0 is connected to the individual input of the flip-flop R1 and the flip-flop R2 FIG. 4B is the circuit diagram with a delay buffer inserted directly before the individual input of the flip-flop R1 and flip-flop R2 in order to assure the hold time. FIG. 4C is the circuit diagram with a delay buffer inserted directly after the output of the flip-flop R0. That is, when compensating the hold time by insertion of a delay buffer, there are several insertion positions to obtain the same effect and the number of required buffers differs depending on the position of insertion.
In an actual design, since the problems mentioned in the above examples arise in combination, it is generally difficult to find the most appropriate positions of insertion by manual operation.
By using the circuit example of FIGS. 5A to 5C, for example, it will be thought over which influence is exerted upon other paths by inserting a delay buffer into a certain path. FIG. 5A shows the original circuit before the insertion of a delay buffer.
Here, after passing through the partial circuit designated with hatched lines in FIG. 5A, the output from the flip-flop R0 is connected to the input of the flip-flop R2 via a logic element U0. Incidentally, the length of delay in this partial circuit is assumed to be large enough to satisfy the hold time. In addition, the output of the flip-flop R1 is connected to the input of the flip-flop R2 via only the logic element U0 alone.
In this example, it is assumed that a hold time violation to input from the flip-flop R1 takes place in the flip-flop R2.
Here, to assure the hold time, it will be considered to insert a delay buffer for the delay-compensation.
First, as shown in FIG. 5B, the case of inserting a buffer directly before the flip-flop R2 will be considered.
Such a connection assures the hold time required for transmission of data from the flip-flop R1 to the flip-flop R2, however at the same time it also lengthens the delay time in the path leading from the flip-flop R0 through the partial circuit designated with hatched lines and the logic element U0 to the flip-flop R2.
If this path is a critical path (i.e., the longest-delay path in the circuit), the possibility of setup time violation comes to appear by contrary. The increase in the delay time of the critical path is a serious problem, because of signifying a decrease in the operating speed of the circuit.
With this example, as shown in FIG. 5C, it becomes the mast desirable connection to insert directly after the flip-flop R1, Furthermore, in the example shown in FIG. 6, there is a path branching from the output of the flip-flop R1, passing through a sufficiently delayed partial circuit and reaching the flip-flop R3, in addition to the example of FIGS. 5A to 5C.
Accordingly, insertion of a delay buffer directly after the output of the flip-flop R1 leads to an increase in the delay of the path from the flip-flop R1 to the flip-flop R3.
Thus, with this circuit, the most desirable position of insertion is existed between a branch J0 and the logic circuit U0.
As mentioned above, it is very difficult to decide the insertion point of a delay buffer to be inserted for the compensation of a hold time violation. At present this operation relies on manpower, but in recent years it has become impossible with a rapid increase in the scale of circuit.